FBDIMM Verification IP

The Perfectus FBDIMM verification IP provides an efficient FBDIMM protocol behavior, between user and DDR2 SDRAM. This verification IP can be used to test the FBDIMM design functionality and reduces design time, design risk, and manufacturing costs for SOC designs. It supports longer idle system Latency, but much higher pin-bandwidth.

Product Component

• Verification Engine
• OCP Bus Functional Models
• FBDIMM Golden Reference Model
• FBDIMM Model with AMB
• Directed & Random tests generator
• FBDIMM Compliance Test Suite
• SystemVerilog Assertions
• Error injector
• Report generator
• Transaction generator
• Protocol Checker
• Protocol Monitor

For more information on each component and evaluation copy please email to: info@perfectus.com