AMB Verification
IP
The Perfectus AMB verification IP
provides an efficient interface behavior, between user
and DDR2 SDRAM. This verification IP can be used to
test the design functionality and reduces design time,
design risk, and manufacturing costs for SOC designs.
The AMB model supports FB-DIMM Channel Protocols and
provision for extending the memory. AMB Model consists
of two FBD links, one DDR2 channel and an SMBus interface.
This model can efficiently handle all the Southbound
& Northbound traffic.
Product Components
- AMB Golden Reference Model
- FBDIMM Models with AMB
- Directed & Random tests
generator
- Compliance Test Suite
- SystemVerilog Assertions
- Error injector
- Report generator
- Transaction generator
- Protocol Checker
- Protocol Monitor
For
more information on each component and evaluation copy
please email to: info@perfectus.com
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